crawler: --no-cover, --concurrency, drop cross-host sleep + batch-50 Step 1 done

Three crawler ergonomics for batch operations:

--no-cover  Skip cover image download. For scan-only modes (license/meta
            scrape) this drops ~1.3s/project and avoids slow-CDN hangs.

--concurrency N  ThreadPoolExecutor wrapping the per-project loop. Default
                 1 = serial (current behavior). Anonymous endpoints tolerate
                 5+ comfortably; output uses a print lock for readable
                 interleaved progress. fetch_cover plumbs through crawl_one.

Drop cross-host sleep #1: in crawl_one between detail HTML (oshwhub.com)
and cover image (image.lceda.cn). Different hosts — sleep was unnecessary.
Saves ~1s/project. Sleep #2 (post-cover, before next iteration) stays — it
gates the next oshwhub.com hit.

download_to gains max_seconds wall budget (default 60s, cover uses 15s).
Defends against pathologically slow CDN connections — observed 10 KB/s
on image.lceda.cn for one project, would have hung 6+ min on a 3.6 MB
cover otherwise. httpx default timeout resets per chunk, so streaming
downloads need an external wall-clock guard.

batch-50 Step 1 (license/meta scrape) shipped:
  50/50 candidates have metadata.json + license recorded
  License distribution: GPL 3.0 32, Public Domain 6, NC variants 8,
                        CERN-OHL 1, MIT 1, CC BY 3.0 1
  Forge-friendly (non-NC): 41/50 (82%)
  Declared attachments: 180 files / 2.36 GB (median 18 MB/proj, max 304 MB)
  Walltime: 3min 26s for 28 projects at concurrency=5 (server-side
            HTML render bound, not sleep-bound)

One orphan partial cover (a670e60a...) cleaned up — leftover from the
first aborted run before the timeout fix landed.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

data/raw/oshwhub/a76c7d50a6c345628eae36dfa7d40541/metadata.json

@@ -0,0 +1,40 @@
+{
+  "source": "oshwhub",
+  "source_url": "https://oshwhub.com/Kirito/dian-sai-shen-qi-FPGA-STM32kai-f",
+  "project_id": "a76c7d50a6c345628eae36dfa7d40541",
+  "title": "电赛神器：FPGA+STM32开发板",
+  "description_short": "本设计为FPGA+STM32开发板，可处理高速信号，带8bit并行高速AD/DA，满足电赛信号类题目设计需要。",
+  "description_path": "description.md",
+  "author": {
+    "username": "Kirito",
+    "display_name": "Kirito",
+    "user_id": "3dc72a434ae74b968d0478d4a9c8724f"
+  },
+  "license": "GPL 3.0",
+  "tags": [],
+  "created_at": "2020-05-16T15:07:18.000Z",
+  "updated_at": "2026-02-04T15:02:47.000Z",
+  "published_at": "2022-07-18T14:13:46.000Z",
+  "crawled_at": "2026-04-28T17:29:51.499025+00:00",
+  "metrics": {
+    "likes": 325,
+    "stars": 801,
+    "forks": 481,
+    "views": 94216,
+    "watch": 0,
+    "comments": 81
+  },
+  "cover": {
+    "url": "https://image.lceda.cn/pullimage/WDKmS7oYUTlDqB4LJ1kZrmEsw8XL4ctqfN9ROn5q.jpeg",
+    "path": null
+  },
+  "files": [],
+  "raw_fields": {
+    "path": "Kirito/dian-sai-shen-qi-FPGA-STM32kai-f",
+    "grade": 4,
+    "origin": "std",
+    "public": true,
+    "publish": true,
+    "skipped_files": []
+  }
+}