Add EasyEDA Std project source ingestion (10 boards backfilled)

打通 oshwhub origin=std 项目的工程源（schematic + PCB dataStr）抓取链路。原 plan.md §1.6 假设需要登录，实测 lceda.cn/api/documents/<doc>?uuid=<doc>&path=<doc> 对公开项目匿名可访问 —— 无需 cookie，无账号封禁风险。调研：4 轮探测留痕在 data/state/std_probe[1-5]/（gitignored）；翻 Std 编辑器 v6.5.51 的 main.min.js bundle 找到 ajaxDetail 端点；按 docType 区分两种响应 shape（schematic 项目视图 vs PCB 文档视图）。 Crawler: - make_source_client() 用浏览器 UA + lceda.cn/editor Referer，因为 oshwhub /api/project/<uuid> 端点拒绝 FacereDataset/0.1 UA（CLAUDE.md UA 例外条款：目标站主动封自定义 UA + 公开静态资源） - fetch_std_source(): 项目元 → version_documents → 逐文档 dataStr → 落 source/<doc>.json + source/manifest.json - --with-source（爬新项目时一并抓源）/ --backfill-source（仅扫已有） - QPS ≤ 0.2 (SLEEP_SOURCE = 5s) 自律 Schema: 加 source_format / source_path / source_documents / editor_version （前 3 进 enum 锁定，便于后续 Pro / KiCad 源对齐）。回填结果：10/10 成功，45 个文档，33.2 MB；schema validate 全通。 docTypes 主要是 1 (schematic) 与 3 (pcb)；USB 电压电流表只有 PCB 文档（4 个：主板+盖板+底板+面板，作者未上传原理图源）。完整调研：docs/sources/easyeda_std_source.md。
2026-04-28 20:07:40 +08:00
parent b0d3afd2a9
commit d874278bc5
71 changed files with 4389 additions and 23 deletions
--- a/data/raw/oshwhub/1a1e865568d04db59a5a140dd3f13581/source/manifest.json
+++ b/data/raw/oshwhub/1a1e865568d04db59a5a140dd3f13581/source/manifest.json
@@ -0,0 +1,155 @@
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