tools/epro2/kicad: Phase-1 .kicad_pcb exporter — 6/6 boards open in KiCad 8
Phase-1 scope: produce a .kicad_pcb that kicad-cli loads cleanly and
that has the right geometry (nets, footprints, tracks, vias, board
outline) — not a 1:1 EDA round-trip. Skipped on purpose for Phase 2:
copper pours (POUR/POURED), manual FILL, teardrops, board-level
strings/images, ARC circle-center recovery.
What lands:
- pcb_writer.write_pcb(): header/general, data-driven layer table
(F.Cu = ord 0; B.Cu = ord 31; SIGNAL inner ids 15+ allocated to
In1.Cu/In2.Cu/... in EPRO2-id sorted order so used inner layers
stay contiguous), net-name → integer id map (id 0 reserved for the
empty net per KiCad convention), LINE→segment / LINE→gr_line on
Edge.Cuts, layer-11 POLY paths walked into Edge.Cuts gr_line chains
(the actual board outline lives on POLY here, not LINE — without
this stats showed edge=0), VIA→via.
- footprint_writer.write_footprint_placement(): inline (footprint ...)
blocks per PCB COMPONENT. EPRO2 RECT/ELLIPSE/OVAL/POLYGON pad
shapes mapped to KiCad rect/circle/oval/custom; SMD vs THT detected
by PAD.hole presence; SLOT holes use (drill oval w h). Pad nets
resolved cross-doc via the existing PCB.PAD_NET → footprint.pad
chain in ProjectRelations. layerId=2 component → (layer B.Cu) +
text on B.SilkS so bottom-side parts render correctly.
Smoke test on ESP-VoCat (6 PCBs): all 6 pass `kicad-cli pcb export svg`
and render. DRC on smallest (MicBoard) reports 145 violations + 75
unconnected — most of the unconnected are GND nets that the EPRO2
source resolves through POUR copper, which Phase 2 will export.
CLI: `python -m tools.epro2.kicad <project> --all-pcb --out <dir>`
emits one .kicad_pcb per PCB doc.
52 → 65 unit tests pass. Float comparisons in tests use math.isclose
because the s-expr 6-decimal trim doesn't preserve strict equality
through `value * MIL_TO_MM` round-trips.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
165
tools/epro2/tests/test_footprint_writer.py
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165
tools/epro2/tests/test_footprint_writer.py
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"""Footprint writer regression: synthetic PCB+FOOTPRINT pair → (footprint ...)."""
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import math
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from tools.epro2.kicad._sexpr_reader import parse
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from tools.epro2.kicad.pcb_writer import MIL_TO_MM, write_pcb
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from tools.epro2.project_relations import ProjectRelations
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from tools.epro2.replay import Document, Project
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def _close(a, b):
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return math.isclose(a, b, abs_tol=1e-6)
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def _block(parsed, name):
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return [c for c in parsed if isinstance(c, list) and c and c[0] == name]
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def _build(fp_objs: list[tuple[str, dict]],
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pcb_objs: list[tuple[str, dict]],
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comp_id: str = "C1",
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fp_uuid: str = "FP1") -> str:
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fp = Document(doc_uuid=fp_uuid, doc_type="FOOTPRINT")
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fp.objects["META"] = {"_type": "META", "title": "TestFp"}
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for k, v in fp_objs:
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fp.objects[k] = v
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pcb = Document(doc_uuid="pcb1", doc_type="PCB")
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pcb.head = {"docType": "PCB", "editVersion": "3.2.91"}
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for k, v in pcb_objs:
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pcb.objects[k] = v
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proj = Project(project_uuid="p")
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proj.documents[fp_uuid] = fp
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proj.documents["pcb1"] = pcb
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pr = ProjectRelations.build(proj)
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return write_pcb(pcb, project_relations=pr, board_origin_mm=(0.0, 0.0))
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def test_smd_rect_pad_lands_on_top_copper_mask_and_paste():
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"""A rectangular SMD pad on EPRO2 layer 1 (TOP) must write its layers
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as F.Cu/F.Mask/F.Paste in KiCad — leaving any of those out drops the
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pad from solder mask / paste stencil and the board fails fab."""
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text = _build(
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fp_objs=[
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("p1", {"_type": "PAD", "num": "1", "centerX": 0, "centerY": 0,
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"padAngle": 0, "layerId": 1, "hole": None,
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"defaultPad": {"padType": "RECT", "width": 30, "height": 20},
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"specialPad": []}),
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],
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pcb_objs=[
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("C1", {"_type": "COMPONENT", "x": 100, "y": 100, "angle": 0, "layerId": 1}),
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("a1", {"_type": "ATTR", "parentId": "C1", "key": "Footprint", "value": "FP1"}),
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],
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)
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p = parse(text)
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fp = _block(p, "footprint")[0]
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pads = [c for c in fp if isinstance(c, list) and c[0] == "pad"]
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assert len(pads) == 1
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pad = pads[0]
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assert pad[1] == "1"
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assert pad[2] == "smd"
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assert pad[3] == "rect"
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layers = next(c for c in pad if isinstance(c, list) and c[0] == "layers")
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assert set(layers[1:]) == {"F.Cu", "F.Mask", "F.Paste"}
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def test_pad_with_hole_writes_thru_hole_and_drill():
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"""A PAD with `hole` set is THT — must be `thru_hole`, span `*.Cu` and
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have a `(drill ...)` block. Slot holes additionally need the
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`(drill oval w h)` two-arg form."""
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text = _build(
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fp_objs=[
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("p1", {"_type": "PAD", "num": "1", "centerX": 0, "centerY": 0,
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"padAngle": 0, "layerId": 12,
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"hole": {"holeType": "ROUND", "width": 12, "height": 12},
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"defaultPad": {"padType": "ELLIPSE", "width": 24, "height": 24}}),
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("p2", {"_type": "PAD", "num": "2", "centerX": 50, "centerY": 0,
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"padAngle": 0, "layerId": 12,
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"hole": {"holeType": "SLOT", "width": 30, "height": 12},
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"defaultPad": {"padType": "OVAL", "width": 50, "height": 24}}),
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],
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pcb_objs=[
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("C1", {"_type": "COMPONENT", "x": 100, "y": 100, "angle": 0}),
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("a1", {"_type": "ATTR", "parentId": "C1", "key": "Footprint", "value": "FP1"}),
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],
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)
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p = parse(text)
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fp = _block(p, "footprint")[0]
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pads = [c for c in fp if isinstance(c, list) and c[0] == "pad"]
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assert len(pads) == 2
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by_num = {pad[1]: pad for pad in pads}
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# Round through-hole
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p1 = by_num["1"]
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assert p1[2] == "thru_hole"
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drill1 = next(c for c in p1 if isinstance(c, list) and c[0] == "drill")
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assert _close(drill1[1], 12 * MIL_TO_MM)
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# Slot through-hole
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p2 = by_num["2"]
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drill2 = next(c for c in p2 if isinstance(c, list) and c[0] == "drill")
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assert drill2[1] == "oval"
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assert _close(drill2[2], 30 * MIL_TO_MM)
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assert _close(drill2[3], 12 * MIL_TO_MM)
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def test_pad_net_resolved_via_pad_net_op():
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"""KiCad needs `(net N "name")` on each pad to know which net it
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belongs to. The mapping comes from the PCB-level PAD_NET op (not
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from anything in the footprint), so it has to be pulled cross-doc."""
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text = _build(
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fp_objs=[
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("p1", {"_type": "PAD", "num": "1", "centerX": 0, "centerY": 0,
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"layerId": 1, "hole": None,
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"defaultPad": {"padType": "RECT", "width": 30, "height": 20}}),
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],
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pcb_objs=[
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('["NET","GND"]', {"_type": "NET"}),
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("C1", {"_type": "COMPONENT", "x": 0, "y": 0, "angle": 0}),
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("a1", {"_type": "ATTR", "parentId": "C1", "key": "Footprint", "value": "FP1"}),
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('["PAD_NET","C1","1","p1"]', {"_type": "PAD_NET", "padNet": "GND"}),
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],
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)
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p = parse(text)
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fp = _block(p, "footprint")[0]
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pad = next(c for c in fp if isinstance(c, list) and c[0] == "pad")
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net_block = next(c for c in pad if isinstance(c, list) and c[0] == "net")
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assert net_block[2] == "GND"
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assert net_block[1] >= 1
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def test_component_on_bottom_layer_gets_b_cu_layer():
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"""COMPONENT.layerId=2 places the footprint on B.Cu, with text
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properties moved to B.SilkS / B.Fab. Without this a bottom-side
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component renders on F.Cu and the netlist routes through phantom
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geometry."""
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text = _build(
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fp_objs=[
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("p1", {"_type": "PAD", "num": "1", "centerX": 0, "centerY": 0,
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"layerId": 1, "hole": None,
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"defaultPad": {"padType": "RECT", "width": 30, "height": 20}}),
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],
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pcb_objs=[
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("C1", {"_type": "COMPONENT", "x": 0, "y": 0, "angle": 0, "layerId": 2}),
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("a1", {"_type": "ATTR", "parentId": "C1", "key": "Footprint", "value": "FP1"}),
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],
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)
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p = parse(text)
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fp = _block(p, "footprint")[0]
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layer = next(c for c in fp if isinstance(c, list) and c[0] == "layer")
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assert layer[1] == "B.Cu"
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def test_unresolved_footprint_skipped_with_diagnostic():
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"""A COMPONENT without a Footprint ATTR pointing at a real
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FOOTPRINT doc must be skipped — emitting an empty (footprint ...)
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block would crash kicad-cli on load."""
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pcb = Document(doc_uuid="pcb1", doc_type="PCB")
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pcb.head = {"docType": "PCB", "editVersion": "3.2.91"}
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pcb.objects["C1"] = {"_type": "COMPONENT", "x": 0, "y": 0}
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# No matching FOOTPRINT doc, no Footprint ATTR
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proj = Project(project_uuid="p")
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proj.documents["pcb1"] = pcb
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pr = ProjectRelations.build(proj)
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text = write_pcb(pcb, project_relations=pr)
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p = parse(text)
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assert _block(p, "footprint") == []
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assert getattr(write_pcb, "last_stats").footprints_unresolved == 1
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162
tools/epro2/tests/test_pcb_writer.py
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162
tools/epro2/tests/test_pcb_writer.py
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"""PCB writer regression: synthetic PCB doc → kicad_pcb → re-parse."""
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import math
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from tools.epro2.kicad._sexpr_reader import parse
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from tools.epro2.kicad.pcb_writer import MIL_TO_MM, write_pcb
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from tools.epro2.project_relations import ProjectRelations
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from tools.epro2.replay import Document, Project
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def _close(a, b):
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"""Float-close: 6-decimal s-expr roundtrip can lose strict equality."""
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return math.isclose(a, b, abs_tol=1e-6)
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def _block(parsed, name):
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return [c for c in parsed if isinstance(c, list) and c and c[0] == name]
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def _pcb(objs, doc_uuid="pcb1") -> Document:
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d = Document(doc_uuid=doc_uuid, doc_type="PCB")
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d.head = {"docType": "PCB", "editVersion": "3.2.91"}
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for k, v in objs:
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d.objects[k] = v
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return d
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def _empty_pr(pcb_doc: Document) -> ProjectRelations:
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p = Project(project_uuid="p")
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p.documents[pcb_doc.doc_uuid] = pcb_doc
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return ProjectRelations.build(p)
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def test_writer_emits_header_and_layers():
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d = _pcb([("META", {"_type": "META", "title": "BoardX"})])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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assert p[0] == "kicad_pcb"
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layers = _block(p, "layers")[0]
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# F.Cu is always ordinal 0, B.Cu always 31 — KiCad convention.
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rows = [row for row in layers[1:] if isinstance(row, list)]
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by_name = {r[1]: r[0] for r in rows}
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assert by_name["F.Cu"] == 0
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assert by_name["B.Cu"] == 31
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assert "Edge.Cuts" in by_name
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def test_inner_signal_layers_inserted_in_id_order():
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"""An EPRO2 4-layer board with SIGNAL ids 15 and 16 actually used must
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map to In1.Cu and In2.Cu (in EPRO2-id sorted order) so the PCB
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layer-stack ordering matches the editor's intent."""
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d = _pcb([
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('["LAYER",1]', {"_type": "LAYER", "layerType": "TOP", "use": True}),
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('["LAYER",2]', {"_type": "LAYER", "layerType": "BOTTOM", "use": True}),
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('["LAYER",15]', {"_type": "LAYER", "layerType": "SIGNAL", "use": True}),
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('["LAYER",16]', {"_type": "LAYER", "layerType": "SIGNAL", "use": True}),
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# Drive "used" flag by including a primitive on each inner layer
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("ln1", {"_type": "LINE", "layerId": 15,
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"startX": 0, "startY": 0, "endX": 100, "endY": 0, "width": 6}),
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("ln2", {"_type": "LINE", "layerId": 16,
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"startX": 0, "startY": 0, "endX": 100, "endY": 0, "width": 6}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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rows = [r for r in _block(p, "layers")[0][1:] if isinstance(r, list)]
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cu_layers = [r[1] for r in rows if r[1].endswith(".Cu")]
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assert cu_layers == ["F.Cu", "In1.Cu", "In2.Cu", "B.Cu"]
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def test_nets_get_stable_integer_ids_starting_at_1():
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"""KiCad reserves net id 0 for "no net" — our user-defined nets must
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start at 1 so segments referencing them don't collide with the empty
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net."""
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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('["NET","VCC"]', {"_type": "NET"}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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nets = _block(p, "net")
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by_name = {n[2]: n[1] for n in nets}
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assert by_name[""] == 0
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assert sorted([by_name["GND"], by_name["VCC"]]) == [1, 2]
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def test_segment_emitted_for_copper_line_with_net():
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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("ln1", {"_type": "LINE", "layerId": 1, "netName": "GND", "width": 6,
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"startX": 100, "startY": 200, "endX": 500, "endY": 200}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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segs = _block(p, "segment")
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assert len(segs) == 1
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seg = segs[0]
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start = next(c for c in seg if isinstance(c, list) and c[0] == "start")
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end = next(c for c in seg if isinstance(c, list) and c[0] == "end")
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assert _close(start[1], 100 * MIL_TO_MM)
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assert _close(start[2], 200 * MIL_TO_MM)
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assert _close(end[1], 500 * MIL_TO_MM)
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layer = next(c for c in seg if isinstance(c, list) and c[0] == "layer")
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assert layer[1] == "F.Cu"
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net_ref = next(c for c in seg if isinstance(c, list) and c[0] == "net")
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assert net_ref[1] >= 1
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def test_via_emitted_with_size_and_drill():
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d = _pcb([
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('["NET","SIG"]', {"_type": "NET"}),
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("v1", {"_type": "VIA", "centerX": 100, "centerY": 200,
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"viaDiameter": 24, "holeDiameter": 12, "netName": "SIG"}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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vias = _block(p, "via")
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assert len(vias) == 1
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v = vias[0]
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at = next(c for c in v if isinstance(c, list) and c[0] == "at")
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assert _close(at[1], 100 * MIL_TO_MM)
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size = next(c for c in v if isinstance(c, list) and c[0] == "size")
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assert _close(size[1], 24 * MIL_TO_MM)
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drill = next(c for c in v if isinstance(c, list) and c[0] == "drill")
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assert _close(drill[1], 12 * MIL_TO_MM)
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def test_outline_poly_emitted_as_edge_cuts_lines():
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"""POLY on layer 11 is the board outline and must convert to
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(gr_line ... (layer Edge.Cuts)) chains so KiCad recognises the
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board boundary — without this the board has no Edge.Cuts geometry
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and DRC reports invalid_outline."""
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d = _pcb([
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("p1", {"_type": "POLY", "layerId": 11, "width": 4,
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"path": [0, 0, "L", 1000, 0, 1000, 1000, 0, 1000, 0, 0]}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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lines = _block(p, "gr_line")
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assert len(lines) == 4 # square: 4 sides
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layers = {next(c for c in ln if isinstance(c, list) and c[0] == "layer")[1]
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for ln in lines}
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assert layers == {"Edge.Cuts"}
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def test_zero_length_segment_skipped():
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d = _pcb([
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("ln1", {"_type": "LINE", "layerId": 1, "netName": "GND", "width": 6,
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"startX": 5, "startY": 5, "endX": 5, "endY": 5}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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assert _block(p, "segment") == []
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assert getattr(write_pcb, "last_stats").skipped == 1
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def test_non_pcb_doc_rejected():
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d = Document(doc_uuid="x", doc_type="SCH_PAGE")
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try:
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write_pcb(d)
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except ValueError:
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return
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raise AssertionError("expected ValueError for non-PCB doc")
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