tools/epro2: add std/ writer — EPRO2 → EasyEDA Std-format JSON for downstream
The downstream colleague consumes oshwhub Std (lceda) dict-format JSON,
not KiCad. The EPRO2 decryption part (per-doc plaintext .epro2 streams
in data/raw/<uuid>/source/) is what we already provide; the missing
piece is converting EPRO2 op-streams into the same `dataStr.shape`
tilde-delimited format their parser already speaks.
New tools/epro2/std/ module, peer of tools/epro2/kicad/, kept
deliberately separate so the KiCad path stays untouched:
- pcb_writer.write_pcb_std() — high-fidelity, validated against a Std
PCB sample at data/raw/oshwhub/3e2f893d.../25931ddab8.json. Maps
LINE→TRACK, VIA→VIA, POUR→COPPERAREA (with SVG `M..L..Z` path),
POLY→CIRCLE/SOLIDREGION, COMPONENT+FOOTPRINT→LIB nested with
#@$-separated PADs (placement rotation + translate applied so pad
coords land at PCB-absolute positions). Layer-id mapping (EPRO2 5↔7
flipped vs Std solder/paste, 11→10 outline, 12→11 multi, SIGNAL
inner 15+ → Std 21+) noted inline.
- sch_writer.write_sch_std() — best-effort. Our corpus has zero Std
schematic samples (docType=1) so verb field orders follow the
EasyEDA Std public spec, not direct observation. Emits W (wire),
N (net flag, including the 5-Voltage Global Net Name power-port
pattern), T (text), LIB (placement with #@$-nested PIN/T). If
downstream's parser bails the fix is almost certainly a positional
field tweak, not a re-architecture.
- __main__.py — flat output `<doc_uuid>.json` per doc directly under
--out (mirrors Std's own data layout); --all-pcb / --all-sch / --all.
Smoke test on ESP-VoCat: 6 PCB + 9 SCH = 15 JSON files, libs_unresolved=0
across the board. Compact JSON (separators=(",",":")) matches Std's
single-line format. Numbers use _num() — integers without trailing .0,
floats trimmed.
71 → 82 unit tests pass.
Open questions for downstream: (1) confirm SCH verb field orders, (2)
do they want any of the upstream metadata fields we drop (master,
owner, created_at, etc — those live on the crawler side, not the
schematic itself)?
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
202
tools/epro2/tests/test_std_writers.py
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202
tools/epro2/tests/test_std_writers.py
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"""Std writer regression: synthetic EPRO2 docs → Std-format JSON dicts."""
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import json
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from collections import Counter
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from tools.epro2.project_relations import ProjectRelations
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from tools.epro2.replay import Document, Project
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from tools.epro2.std.pcb_writer import write_pcb_std
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from tools.epro2.std.sch_writer import write_sch_std
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def _doc(typ, uuid="d"):
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d = Document(doc_uuid=uuid, doc_type=typ)
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d.head = {"docType": typ}
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return d
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def _empty_pr(*docs):
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p = Project(project_uuid="p")
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for doc in docs:
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p.documents[doc.doc_uuid] = doc
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return ProjectRelations.build(p)
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def _verbs(payload):
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return Counter(s.split("~")[0] for s in payload["result"]["dataStr"]["shape"])
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# -- PCB ---------------------------------------------------------------
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def test_pcb_envelope_matches_std_shape():
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"""Top-level envelope must be `{success, code, result}` with
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`result.docType == 3` and `result.dataStr.shape` as a list — that's
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the contract Std parsers key off. Anything else and downstream's
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parser bails before the shape array is even read."""
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d = _doc("PCB", "p1")
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d.objects["META"] = {"_type": "META", "title": "Test"}
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payload = write_pcb_std(d, project_relations=_empty_pr(d))
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assert payload["success"] is True
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assert payload["code"] == 0
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r = payload["result"]
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assert r["docType"] == 3
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assert r["uuid"] == "p1"
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assert isinstance(r["dataStr"]["shape"], list)
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# Inner SIGNAL layers extension keeps the layer block consistent
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assert any("TopLayer" in s for s in r["dataStr"]["layers"])
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def test_pcb_line_emits_track_with_layer_and_net():
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"""LINE on a copper layer becomes a Std TRACK string. Field order is
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`TRACK~width~layer~net~points~uuid~locked` — same as Std produces;
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a wrong order means tracks land on the wrong layer in downstream
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renders even if the parser doesn't crash."""
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d = _doc("PCB", "p1")
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d.objects["ln1"] = {
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"_type": "LINE", "layerId": 1, "netName": "GND", "width": 6,
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"startX": 100, "startY": 200, "endX": 500, "endY": 200,
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}
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payload = write_pcb_std(d, project_relations=_empty_pr(d))
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tracks = [s for s in payload["result"]["dataStr"]["shape"] if s.startswith("TRACK~")]
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assert len(tracks) == 1
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fields = tracks[0].split("~")
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assert fields[0] == "TRACK"
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assert fields[1] == "6" # width
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assert fields[2] == "1" # std layer 1 = TopLayer
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assert fields[3] == "GND" # net name
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assert "100 200 500 200" in fields[4]
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def test_pcb_via_emits_correct_field_order():
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d = _doc("PCB", "p1")
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d.objects["v1"] = {
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"_type": "VIA", "centerX": 100, "centerY": 200,
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"viaDiameter": 24, "holeDiameter": 12, "netName": "VCC",
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}
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payload = write_pcb_std(d, project_relations=_empty_pr(d))
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via = next(s for s in payload["result"]["dataStr"]["shape"] if s.startswith("VIA~"))
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f = via.split("~")
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# VIA~x~y~outerD~net~innerD~uuid~locked
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assert f[1] == "100"
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assert f[2] == "200"
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assert f[3] == "24"
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assert f[4] == "VCC"
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assert f[5] == "12"
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def test_pcb_pour_rectangle_becomes_copperarea_with_svg_path():
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"""POUR on a copper layer must emit a COPPERAREA with an SVG `M..L..Z`
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path — Std uses SVG path syntax for filled regions, and downstream
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fills are computed from this path. A `R x y w h` rectangle expands
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to an explicit four-corner Z-closed polygon."""
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d = _doc("PCB", "p1")
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d.objects["p1"] = {
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"_type": "POUR", "layerId": 1, "netName": "GND",
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"path": [["R", 0, 0, 1000, 1000]],
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}
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payload = write_pcb_std(d, project_relations=_empty_pr(d))
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ca = next(s for s in payload["result"]["dataStr"]["shape"] if s.startswith("COPPERAREA~"))
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assert "M 0 0" in ca
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assert " Z" in ca
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assert "GND" in ca
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def test_pcb_lib_nests_pads_via_separator():
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"""A footprint placement must emit a LIB outer string with PAD inner
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shapes joined by `#@$` — that's how Std writes one symbol-with-pads
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per shape entry. If we emit pads as separate top-level shapes,
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downstream's symbol-grouping breaks (pads end up unowned)."""
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fp = _doc("FOOTPRINT", "fp1")
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fp.objects["META"] = {"_type": "META", "title": "0402"}
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fp.objects["pad1"] = {
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"_type": "PAD", "num": "1", "centerX": -20, "centerY": 0,
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"padAngle": 0, "layerId": 1, "hole": None,
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"defaultPad": {"padType": "RECT", "width": 30, "height": 20},
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}
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pcb = _doc("PCB", "pcb1")
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pcb.objects["C1"] = {"_type": "COMPONENT", "x": 100, "y": 100, "angle": 0}
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pcb.objects["a1"] = {
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"_type": "ATTR", "parentId": "C1", "key": "Footprint", "value": "fp1",
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}
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payload = write_pcb_std(pcb, project_relations=_empty_pr(fp, pcb))
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libs = [s for s in payload["result"]["dataStr"]["shape"] if s.startswith("LIB~")]
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assert len(libs) == 1
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# Nested children separated by '#@$'
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parts = libs[0].split("#@$")
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assert parts[0].startswith("LIB~")
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assert any(p.startswith("PAD~") for p in parts[1:])
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# Std treats each LIB-rooted block as the unit shape entry, not the
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# nested PADs — verify no top-level PAD leaked
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assert not any(s.startswith("PAD~") for s in payload["result"]["dataStr"]["shape"])
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# -- SCH ---------------------------------------------------------------
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def test_sch_envelope_carries_doctype_1():
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"""Std schematic docs are docType=1. Downstream filters on this to
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pick which parser to invoke (PCB parser vs SCH parser); a wrong
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docType silently routes the file to the wrong parser."""
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d = _doc("SCH_PAGE", "s1")
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d.objects["META"] = {"_type": "META", "title": "Test"}
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payload = write_sch_std(d, project_relations=_empty_pr(d))
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assert payload["result"]["docType"] == 1
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def test_sch_named_wire_emits_wire_plus_netflag():
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"""A LINE whose lineGroup carries a NET attr must produce both a W
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(the wire segment) and an N (a net flag at one endpoint, named
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after the net). Same-named flags on distinct wire segments is how
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Std unifies named nets — without the N, the wire is anonymous."""
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d = _doc("SCH_PAGE", "s1")
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d.objects["w1"] = {"_type": "WIRE"}
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d.objects["a1"] = {"_type": "ATTR", "parentId": "w1", "key": "NET", "value": "GND"}
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d.objects["ln1"] = {
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"_type": "LINE", "lineGroup": "w1",
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"startX": 0, "startY": 0, "endX": 100, "endY": 0,
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}
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payload = write_sch_std(d, project_relations=_empty_pr(d))
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v = _verbs(payload)
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assert v["W"] == 1
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assert v["N"] == 1
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def test_sch_power_port_component_emits_extra_netflag():
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"""The 5-Voltage / generic placeholder COMPONENT (Global Net Name
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ATTR carries the rail name) must emit an N flag at the placement
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so the symbol's pin connects to the global rail. Same fix as the
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KiCad path's global_label handling."""
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sym = _doc("SYMBOL", "sym1")
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sym.objects["pid8a0e77bacb214e"] = {"_type": "PART", "title": ""}
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sym.objects["pin1"] = {
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"_type": "PIN", "partId": "pid8a0e77bacb214e",
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"x": 0, "y": 0, "length": 5, "rotation": 0,
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}
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sch = _doc("SCH_PAGE", "s1")
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sch.objects["e1"] = {
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"_type": "COMPONENT", "partId": "pid8a0e77bacb214e",
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"x": 100, "y": 50, "rotation": 0,
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}
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sch.objects["a1"] = {
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"_type": "ATTR", "parentId": "e1",
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"key": "Global Net Name", "value": "VBUS",
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}
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payload = write_sch_std(sch, project_relations=_empty_pr(sym, sch))
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flags = [s for s in payload["result"]["dataStr"]["shape"] if s.startswith("N~")]
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assert any("VBUS" in s for s in flags), \
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"expected an N flag named VBUS for the power-port placement"
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def test_writers_round_trip_through_json_dump():
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"""Whatever we build has to survive json.dumps without errors —
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ints/floats/strings/lists only, no datetime / Decimal / bytes
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sneaking in. Catches type leaks early."""
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d = _doc("PCB", "p1")
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d.objects["META"] = {"_type": "META", "title": "Test"}
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payload = write_pcb_std(d, project_relations=_empty_pr(d))
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json.dumps(payload)
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d2 = _doc("SCH_PAGE", "s1")
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d2.objects["META"] = {"_type": "META", "title": "Test"}
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payload2 = write_sch_std(d2, project_relations=_empty_pr(d2))
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json.dumps(payload2)
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