Bisect found two semantics mismatches between EPRO2 and KiCad that cause the 850 real-connectivity ERC violations on the ESP-VoCat ref project: 1. sym_writer was emitting lib coords without negating Y, but KiCad lib uses Y-up and re-flips Y on placement (Y-down schematic). So vertically arranged pins ended up at Y-mirrored absolute positions and wires that reach the geometric pin tip in EPRO2 missed the rendered pin tip in KiCad. Fix: lib_y = -epro2_y, lib_rot = (360 - rot) % 360 for pin/text. 2. sch_writer was treating each LINE as an isolated wire — but EPRO2 binds segments into nets by NAME (WIRE.NET attr), not just geometry. Multi-segment nets like GND/VBUS show up as N disconnected stubs to KiCad. Fix: per-LINE, look up lineGroup → WIRE → NET attr and emit a `(label "<NET>")` at the LINE's start. Same-named labels on distinct physical wires is how KiCad's ERC recognizes a multi-segment net. ESP-VoCat 9 sheets: wire_dangling 444 → 52 (-88%) pin_not_connected 406 → 196 (-52%) real connectivity total 850 → 248 (-71%) Why we did NOT round to grid (the obvious-looking fix): EPRO2 places some pins on a 10-mil pitch (e.g. magnetic socket); rounding to KiCad's default 50-mil ERC grid would collapse those pins. The 248 residual is fundamentally cross-sheet — single-sheet ERC can't see a net's other endpoints on sibling sheets — and is a Phase-3 (hierarchical sheet) problem, not a per-sheet one. 41 → 46 unit tests pass. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
150 lines
5.4 KiB
Python
150 lines
5.4 KiB
Python
"""Schematic writer regression: synthetic SCH_PAGE → kicad_sch → re-parse."""
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from tools.epro2.kicad._sexpr_reader import parse
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from tools.epro2.kicad.sch_writer import MIL_TO_MM, write_sch_page
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from tools.epro2.replay import Document
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def _doc(objs, doc_uuid="d_test"):
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d = Document(doc_uuid=doc_uuid, doc_type="SCH_PAGE")
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d.head = {"docType": "SCH_PAGE", "editVersion": "3.2.91"}
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for k, v in objs:
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d.objects[k] = v
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return d
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def _block(parsed, name):
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"""Return all top-level child blocks of a kicad_sch named ``name``."""
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return [c for c in parsed if isinstance(c, list) and c and c[0] == name]
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def test_writer_emits_paper_title_and_lib_symbols():
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d = _doc([("META", {"_type": "META", "title": "Test"})])
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text = write_sch_page(d)
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p = parse(text)
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assert p[0] == "kicad_sch"
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assert _block(p, "paper")[0][1] == "A4"
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title = _block(p, "title_block")[0]
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assert title[1] == ["title", "Test"]
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# lib_symbols stub present (Phase 1)
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assert _block(p, "lib_symbols") == [["lib_symbols"]]
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def test_wires_emit_one_block_per_line_with_mil_to_mm_conversion():
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d = _doc([
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("ln1", {"_type": "LINE", "lineGroup": "w1",
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"startX": 0, "startY": 0, "endX": 1000, "endY": 0}),
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])
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text = write_sch_page(d, sheet_origin_mm=(0.0, 0.0))
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p = parse(text)
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wires = _block(p, "wire")
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assert len(wires) == 1
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pts = wires[0][1] # ['pts', ['xy', x1, y1], ['xy', x2, y2]]
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assert pts[0] == "pts"
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assert pts[1][1:] == [0.0, 0.0]
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assert pts[2][1] == 1000 * MIL_TO_MM # 25.4 mm
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assert pts[2][2] == 0.0
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assert getattr(write_sch_page, "last_stats").wires == 1
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def test_zero_length_wire_skipped():
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d = _doc([
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("ln1", {"_type": "LINE", "startX": 5, "startY": 5, "endX": 5, "endY": 5}),
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])
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text = write_sch_page(d)
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p = parse(text)
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assert _block(p, "wire") == []
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stats = getattr(write_sch_page, "last_stats")
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assert stats.wires == 0
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assert stats.skipped == 1
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def test_component_emits_symbol_placement_with_designator():
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d = _doc([
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("e1", {"_type": "COMPONENT", "partId": "MyPart.1",
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"x": 100, "y": 200, "rotation": 90}),
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("a1", {"_type": "ATTR", "parentId": "e1",
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"key": "Designator", "value": "R1"}),
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("a2", {"_type": "ATTR", "parentId": "e1",
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"key": "Value", "value": "10kΩ"}),
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])
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text = write_sch_page(d, sheet_origin_mm=(0.0, 0.0))
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p = parse(text)
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syms = _block(p, "symbol")
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assert len(syms) == 1
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sym = syms[0]
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# lib_id contains our partId
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lib_id = next(c for c in sym if isinstance(c, list) and c[0] == "lib_id")
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assert "MyPart.1" in lib_id[1]
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# at xy applied
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at = next(c for c in sym if isinstance(c, list) and c[0] == "at")
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assert at[1] == 100 * MIL_TO_MM
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assert at[2] == 200 * MIL_TO_MM
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assert at[3] == 90.0
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# properties carry ATTR values
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props = [c for c in sym if isinstance(c, list) and c[0] == "property"]
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by_name = {p[1]: p[2] for p in props}
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assert by_name["Reference"] == "R1"
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assert by_name["Value"] == "10kΩ"
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def test_text_object_emits_text_block_when_non_empty():
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d = _doc([
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("t1", {"_type": "TEXT", "value": "Hello", "x": 50, "y": 50}),
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("t2", {"_type": "TEXT", "value": "", "x": 60, "y": 60}), # skipped
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])
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text = write_sch_page(d, sheet_origin_mm=(0.0, 0.0))
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p = parse(text)
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texts = _block(p, "text")
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assert len(texts) == 1
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assert texts[0][1] == "Hello"
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def test_named_wire_emits_label_at_line_start():
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"""EPRO2 binds wire segments into nets by NAME (WIRE.NET attr), not by
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geometry alone. Each LINE whose lineGroup points to a WIRE with a NET
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attr must get a (label "<NET>") at one endpoint — same-named labels on
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distinct LINEs are how KiCad's ERC recognizes a multi-segment net."""
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d = _doc([
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("w1", {"_type": "WIRE"}),
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("a1", {"_type": "ATTR", "parentId": "w1", "key": "NET", "value": "GND"}),
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("ln1", {"_type": "LINE", "lineGroup": "w1",
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"startX": 100, "startY": 0, "endX": 200, "endY": 0}),
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("ln2", {"_type": "LINE", "lineGroup": "w1",
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"startX": 300, "startY": 0, "endX": 400, "endY": 0}),
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])
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text = write_sch_page(d, sheet_origin_mm=(0.0, 0.0))
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p = parse(text)
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labels = _block(p, "label")
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assert len(labels) == 2 # one label per non-degenerate LINE
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assert all(lab[1] == "GND" for lab in labels)
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# First label sits at the first LINE's start endpoint
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at = next(c for c in labels[0] if isinstance(c, list) and c[0] == "at")
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assert at[1] == 100 * MIL_TO_MM
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assert at[2] == 0.0
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assert getattr(write_sch_page, "last_stats").labels == 2
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def test_unnamed_wire_emits_no_label():
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"""A WIRE without a NET attr (or a LINE without a lineGroup) gets no
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label — emitting a label without a name would be syntactically invalid
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and semantically meaningless."""
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d = _doc([
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("w1", {"_type": "WIRE"}), # no NET attr
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("ln1", {"_type": "LINE", "lineGroup": "w1",
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"startX": 0, "startY": 0, "endX": 100, "endY": 0}),
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])
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text = write_sch_page(d, sheet_origin_mm=(0.0, 0.0))
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p = parse(text)
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assert _block(p, "label") == []
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assert getattr(write_sch_page, "last_stats").labels == 0
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def test_non_sch_page_doc_rejected():
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d = Document(doc_uuid="x", doc_type="PCB")
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try:
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write_sch_page(d)
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except ValueError:
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return
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raise AssertionError("expected ValueError for non-SCH_PAGE doc")
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