Run on dev1 (Guangzhou) for the latency advantage. Walltime 3:41 vs
Singapore-estimated 1-2h (~30x speedup, mostly from image.lceda.cn
RTT going from 263ms to 2.6ms).
Pro 25: 24 ok + 1 fail (Super Dial 7f7565ef11 — Pro 2.x legacy
schematic/lists 401, separate cookie-perm issue)
611 docs, 31 MB total
Std 25: 25 ok, 97 docs, 74 MB total
Combined: 49/50 success, 708 docs, 105 MB new disk usage
--max-source-mb 200 cap was not tripped; the 25 Pro candidates are all
under 10 MB, so the 481 MB X86-board outlier from the original sample
was not representative.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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4 lines
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{"type":"DOCHEAD","ticket":396}||{"docType":"DEVICE","client":"4d32fc57-d8c1-42a9-b5b1-ef12efa00ebe","uuid":"68afea56b3204224a32e32fa41caf046","updateTime":1734253601000,"version":"1653291699","user":{"uuid":"f5e5983cd8e94ba3b7f01b6e21d709b8","nickname":"Sngels_wyh","username":"sngelswyh","avatar":"//image.lceda.cn/avatars/2024/12/s9etBtOA1q39LNLVZsfmkSrhj2DlgmIL2wFnv7f1.webp"}}|
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{"type":"META","ticket":397,"id":"META"}||{"title":"HDR-M_2.54-1x9P","tags":["连接器","排针"],"source":"e79e45a4d1984c3c84e9869a113c23cb|0819f05c4eef4c71ace90d822a990e87","images":[""],"attributes":{"Convert to PCB":"yes","Add into BOM":"yes","Designator":"H?","Supplier Part":"C492408","Supplier Footprint":"插件","Symbol":"41b723b8af6d493da3493fcc6dd84b99","Footprint":"8c27474f4ce6499ab988c2c3cb7e61c1","3D Model":"b5c1e988b3bb4503807579736b357ad0","3D Model Title":"HDR-TH_9P-P2.54-M-LI-1X9P","3D Model Transform":"890.15562,98.425,0,0,0,0,0,0,-118.11","Description":""}}|
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