Knowit
adc5dc5e1b
Phase-1 left 75-358 unconnected_items per board (DRC), dominated by
GND/AGND/POWER nets that EPRO2 routes through copper pour, not discrete
traces. Phase-2 lands those:
- pcb_writer._decode_zone_path handles the three POUR.path encodings
seen in ESP-VoCat: rectangle (['R', x, y, w, h, ...]), circle
(['CIRCLE', cx, cy, r]) approximated as a 36-segment polygon, and
polyline (numeric pairs with 'L'/'ARC' verb tokens).
- Each POUR on a copper layer turns into a (zone (polygon ...) ...)
block plus a (filled_polygon ...) that mirrors the boundary.
Why mirror, not auto-fill: kicad-cli pcb drc does NOT run the zone
filler before checking — only the KiCad GUI does. Without a
pre-computed (filled_polygon ...), DRC sees zones as empty regions and
reports the entire net as unconnected. Mirroring the boundary as the
fill is "connectivity-correct, clearance-imprecise" — KiCad users can
still hit Edit > Fill Zones to refine thermals and pad clearances. We
chose this over reading EPRO2's POURED.pourFill (the editor's own
post-fill polygons) because POURED paths use ARC tokens we'd need to
fully decode, and the user-drawn POUR boundary is already the
authoritative "intended copper" region.
ESP-VoCat DRC totals: 883 → 730 unconnected_items (-17% project-wide).
CoreBoard, the 4-layer board with the most pour coverage, drops 358 →
205 (-43%). Other boards see no movement because their unconnected
items are non-pour issues — pads outside the user-drawn POUR
rectangle, or internal $1N nets via vias on the wrong net (separate
problem, separate fix).
65 → 68 unit tests pass.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
224 lines
9.0 KiB
Python
224 lines
9.0 KiB
Python
"""PCB writer regression: synthetic PCB doc → kicad_pcb → re-parse."""
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import math
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from tools.epro2.kicad._sexpr_reader import parse
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from tools.epro2.kicad.pcb_writer import MIL_TO_MM, write_pcb
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from tools.epro2.project_relations import ProjectRelations
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from tools.epro2.replay import Document, Project
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def _close(a, b):
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"""Float-close: 6-decimal s-expr roundtrip can lose strict equality."""
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return math.isclose(a, b, abs_tol=1e-6)
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def _block(parsed, name):
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return [c for c in parsed if isinstance(c, list) and c and c[0] == name]
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def _pcb(objs, doc_uuid="pcb1") -> Document:
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d = Document(doc_uuid=doc_uuid, doc_type="PCB")
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d.head = {"docType": "PCB", "editVersion": "3.2.91"}
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for k, v in objs:
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d.objects[k] = v
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return d
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def _empty_pr(pcb_doc: Document) -> ProjectRelations:
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p = Project(project_uuid="p")
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p.documents[pcb_doc.doc_uuid] = pcb_doc
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return ProjectRelations.build(p)
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def test_writer_emits_header_and_layers():
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d = _pcb([("META", {"_type": "META", "title": "BoardX"})])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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assert p[0] == "kicad_pcb"
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layers = _block(p, "layers")[0]
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# F.Cu is always ordinal 0, B.Cu always 31 — KiCad convention.
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rows = [row for row in layers[1:] if isinstance(row, list)]
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by_name = {r[1]: r[0] for r in rows}
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assert by_name["F.Cu"] == 0
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assert by_name["B.Cu"] == 31
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assert "Edge.Cuts" in by_name
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def test_inner_signal_layers_inserted_in_id_order():
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"""An EPRO2 4-layer board with SIGNAL ids 15 and 16 actually used must
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map to In1.Cu and In2.Cu (in EPRO2-id sorted order) so the PCB
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layer-stack ordering matches the editor's intent."""
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d = _pcb([
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('["LAYER",1]', {"_type": "LAYER", "layerType": "TOP", "use": True}),
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('["LAYER",2]', {"_type": "LAYER", "layerType": "BOTTOM", "use": True}),
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('["LAYER",15]', {"_type": "LAYER", "layerType": "SIGNAL", "use": True}),
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('["LAYER",16]', {"_type": "LAYER", "layerType": "SIGNAL", "use": True}),
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# Drive "used" flag by including a primitive on each inner layer
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("ln1", {"_type": "LINE", "layerId": 15,
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"startX": 0, "startY": 0, "endX": 100, "endY": 0, "width": 6}),
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("ln2", {"_type": "LINE", "layerId": 16,
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"startX": 0, "startY": 0, "endX": 100, "endY": 0, "width": 6}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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rows = [r for r in _block(p, "layers")[0][1:] if isinstance(r, list)]
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cu_layers = [r[1] for r in rows if r[1].endswith(".Cu")]
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assert cu_layers == ["F.Cu", "In1.Cu", "In2.Cu", "B.Cu"]
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def test_nets_get_stable_integer_ids_starting_at_1():
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"""KiCad reserves net id 0 for "no net" — our user-defined nets must
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start at 1 so segments referencing them don't collide with the empty
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net."""
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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('["NET","VCC"]', {"_type": "NET"}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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nets = _block(p, "net")
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by_name = {n[2]: n[1] for n in nets}
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assert by_name[""] == 0
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assert sorted([by_name["GND"], by_name["VCC"]]) == [1, 2]
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def test_segment_emitted_for_copper_line_with_net():
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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("ln1", {"_type": "LINE", "layerId": 1, "netName": "GND", "width": 6,
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"startX": 100, "startY": 200, "endX": 500, "endY": 200}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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segs = _block(p, "segment")
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assert len(segs) == 1
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seg = segs[0]
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start = next(c for c in seg if isinstance(c, list) and c[0] == "start")
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end = next(c for c in seg if isinstance(c, list) and c[0] == "end")
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assert _close(start[1], 100 * MIL_TO_MM)
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assert _close(start[2], 200 * MIL_TO_MM)
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assert _close(end[1], 500 * MIL_TO_MM)
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layer = next(c for c in seg if isinstance(c, list) and c[0] == "layer")
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assert layer[1] == "F.Cu"
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net_ref = next(c for c in seg if isinstance(c, list) and c[0] == "net")
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assert net_ref[1] >= 1
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def test_via_emitted_with_size_and_drill():
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d = _pcb([
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('["NET","SIG"]', {"_type": "NET"}),
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("v1", {"_type": "VIA", "centerX": 100, "centerY": 200,
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"viaDiameter": 24, "holeDiameter": 12, "netName": "SIG"}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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vias = _block(p, "via")
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assert len(vias) == 1
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v = vias[0]
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at = next(c for c in v if isinstance(c, list) and c[0] == "at")
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assert _close(at[1], 100 * MIL_TO_MM)
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size = next(c for c in v if isinstance(c, list) and c[0] == "size")
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assert _close(size[1], 24 * MIL_TO_MM)
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drill = next(c for c in v if isinstance(c, list) and c[0] == "drill")
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assert _close(drill[1], 12 * MIL_TO_MM)
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def test_outline_poly_emitted_as_edge_cuts_lines():
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"""POLY on layer 11 is the board outline and must convert to
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(gr_line ... (layer Edge.Cuts)) chains so KiCad recognises the
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board boundary — without this the board has no Edge.Cuts geometry
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and DRC reports invalid_outline."""
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d = _pcb([
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("p1", {"_type": "POLY", "layerId": 11, "width": 4,
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"path": [0, 0, "L", 1000, 0, 1000, 1000, 0, 1000, 0, 0]}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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lines = _block(p, "gr_line")
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assert len(lines) == 4 # square: 4 sides
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layers = {next(c for c in ln if isinstance(c, list) and c[0] == "layer")[1]
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for ln in lines}
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assert layers == {"Edge.Cuts"}
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def test_zero_length_segment_skipped():
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d = _pcb([
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("ln1", {"_type": "LINE", "layerId": 1, "netName": "GND", "width": 6,
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"startX": 5, "startY": 5, "endX": 5, "endY": 5}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d))
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p = parse(text)
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assert _block(p, "segment") == []
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assert getattr(write_pcb, "last_stats").skipped == 1
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def test_pour_rectangle_emits_zone_with_filled_polygon():
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"""An EPRO2 POUR with rectangle path on a copper layer must turn into
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a (zone) with both a (polygon ...) boundary and a (filled_polygon ...)
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that mirrors it. Without the filled_polygon, kicad-cli pcb drc never
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runs the zone filler and reports the entire net as unconnected."""
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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("p1", {"_type": "POUR", "layerId": 1, "netName": "GND",
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"path": [["R", 0, 0, 1000, 1000, 0, 0]]}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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zones = _block(p, "zone")
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assert len(zones) == 1
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z = zones[0]
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layer = next(c for c in z if isinstance(c, list) and c[0] == "layer")
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assert layer[1] == "F.Cu"
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net_name = next(c for c in z if isinstance(c, list) and c[0] == "net_name")
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assert net_name[1] == "GND"
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poly = next(c for c in z if isinstance(c, list) and c[0] == "polygon")
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pts = next(c for c in poly if isinstance(c, list) and c[0] == "pts")
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xys = [c for c in pts if isinstance(c, list) and c[0] == "xy"]
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assert len(xys) == 4 # rectangle has 4 corners
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filled = next(c for c in z if isinstance(c, list) and c[0] == "filled_polygon")
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fpts = next(c for c in filled if isinstance(c, list) and c[0] == "pts")
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assert len([c for c in fpts if isinstance(c, list) and c[0] == "xy"]) == 4
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def test_pour_circle_path_sampled_to_polygon():
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"""Circular POURs on copper layers must be approximated as a polygon —
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KiCad zones don't accept (circle ...) primitives, so the fill region
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needs explicit (xy) points around the circumference."""
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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("p1", {"_type": "POUR", "layerId": 1, "netName": "GND",
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"path": [["CIRCLE", 0, 0, 100]]}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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z = _block(p, "zone")[0]
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poly = next(c for c in z if isinstance(c, list) and c[0] == "polygon")
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pts = next(c for c in poly if isinstance(c, list) and c[0] == "pts")
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xys = [c for c in pts if isinstance(c, list) and c[0] == "xy"]
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# 36 segments by default — enough to approximate a circle for fill
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assert len(xys) >= 12
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def test_pour_on_non_copper_layer_skipped():
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"""POURs only make sense as copper zones; an EPRO2 POUR mistakenly
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landed on a silk layer must NOT emit (zone ...) since KiCad zones
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are copper-only and the file would be semantically wrong."""
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d = _pcb([
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('["NET","GND"]', {"_type": "NET"}),
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("p1", {"_type": "POUR", "layerId": 3, "netName": "GND",
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"path": [["R", 0, 0, 100, 100]]}),
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])
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text = write_pcb(d, project_relations=_empty_pr(d), board_origin_mm=(0.0, 0.0))
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p = parse(text)
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assert _block(p, "zone") == []
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def test_non_pcb_doc_rejected():
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d = Document(doc_uuid="x", doc_type="SCH_PAGE")
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try:
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write_pcb(d)
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except ValueError:
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return
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raise AssertionError("expected ValueError for non-PCB doc")
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