Knowit ff5553fb06 tools/epro2/kicad: hierarchical export + global_label + 5-Voltage power ports
Three coupled changes so kicad-cli sch erc runs at the project level
(across all sheets of one schematic) instead of single-sheet:

1. (label) → (global_label (shape passive)). EPRO2 nets are
   project-global by construction (named rails span every page in the
   SCH and physically wire across PCBs); KiCad's local label is sheet-
   scoped and triggers `label_dangling` for any name not duplicated on
   the same page.

2. New root_sch_writer that groups SCH_PAGE docs by their parent SCH
   (META.schematic), emits one root .kicad_sch per group with one
   (sheet ...) entry per child, and threads the root-assigned uuid back
   into each child's (sheet_instances) so KiCad can bind them.
   --all-sch now defaults to this; --flat falls back to one-file-per-page.

3. EPRO2's "5-Voltage" placeholder COMPONENT (partId
   pid8a0e77bacb214e, 365 instances on ESP-VoCat) is the editor's power
   port. The rail name lives in the placement's `Global Net Name` ATTR,
   not in the PART. We now emit a (global_label "<rail>") at the
   placement coords whenever that attr is set (101/365 of them on
   ESP-VoCat — the rest are unconfigured drafts).

ESP-VoCat 5 hierarchical roots: 2325 → 2265 violations. Modest because
5 of 6 SCHs are single-page (no cross-sheet nets to resolve), and the
one 4-page schematic (CoreBoard) shares only a handful of names across
sheets — most net names are de-facto sheet-local. The remaining ~190
pin_not_connected are dominated by 0402-style passives whose pin tip
lies on a wire's interior, not at an endpoint; KiCad needs an explicit
(junction) at those points and we don't yet emit one. Marked as the
next follow-up in log.md.

47 → 52 unit tests pass.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-04-29 00:05:47 +08:00
2026-04-26 11:54:01 +08:00
2026-04-23 23:42:21 +08:00
2026-04-26 11:54:01 +08:00

FacereDataset

Facere 专有模型训练与硬件设计知识库提供数据支撑的开源硬件设计数据集。

目标

采集、清洗、结构化互联网公开可用的硬件设计资产原理图、PCB、BOM、Gerber、3D 模型、固件、文档),输出:

  1. 训练数据集:可直接喂给 LLM / 多模态模型做预训练、SFT、RAG 的结构化语料。
  2. 检索型知识库:按元器件、拓扑、应用领域可查的设计参考库。
  3. 派生产物元件封装库、常见子电路模板、BOM 成本曲线等。

数据来源(第一批)

站点 URL 覆盖 许可 复杂度 登录态
立创开源平台 oshwhub.com 12 493 公开项目(附件 + 元数据) GPL 3.0 / Public Domain / CC-BY-SA 为主 不需要
立创 EDA 工程源 u.lceda.cn 原理图 + PCB + 组件 JSON 同 oshwhub 项目 需要(合法账号,见 CLAUDE.md
HF bshada/open-schematics huggingface.co 10K+ KiCad 已预处理 schematics CC-BY-4.0 极低(整包镜像) 不需要
GitHub github.com KiCad / EasyEDA repo 各 repo 自定 gh API 不需要
Hackaday.io hackaday.io 项目叙事 + 文件 作者自定 不需要
CERN OHR ohwr.org 高质量工业级 CERN-OHL 不需要
Wikifactory wikifactory.com 社区项目 作者自定 不需要

运行环境:专用云服务器(广州),登录凭据集中在 ~/.secrets/。详情见 docs/infra.md(部署后创建)。

详细爬取计划见 plan.md;当前已入库项目清单见 projects.md

仓库结构

FacereDataset/
├── README.md        项目简介(本文件)
├── CLAUDE.md        Claude Code 项目级指令
├── plan.md          分阶段爬取与处理计划
├── log.md           执行日志(时间倒序)
├── crawlers/        各站点爬虫(一站一子包)
├── schemas/         统一数据 schemaproject.schema.json
├── scripts/         去重、格式转换、完整性校验工具
├── data/            数据产出raw/ processed/,大文件走 LFS 或外部存储)
└── docs/            设计笔记、法律合规、数据字典

合法与伦理

  • 产出结果用于研究,不公开,不再分发
  • 只抓取公开可访问、标注为开源或明确允许再分发的内容。
  • 每条记录保留 source_urlauthorlicensecrawled_at 作溯源。
  • 后续按许可证逐条核对清洗CC-BY 要求署名CC-BY-SA 要求同许可分享,等)。

快速开始

# 克隆
git clone https://git.deepknow.site/Facere/FacereDataset.git
cd FacereDataset

# 安装Python 3.11+uv
uv sync

# 运行某个爬虫
uv run python -m crawlers.oshwhub --limit 10

当前处于骨架初始化阶段,爬虫尚未实现。见 plan.md Phase 1。

维护

  • 主要维护者Charlesgit.deepknow.site/Knowit
  • 远端:git.deepknow.site/Facere/FacereDataset
  • 问题追踪Gitea Issues
Description
爬取立创开源平台等互联网公开硬件设计,作为数据库与专有模型训练数据集,为Facere提供数据支持
Readme 783 MiB
2026-04-30 19:15:55 +08:00
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Python 100%